View MP3275_954623.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MP3275
Fault Protected 16 Channel, 12-Bit Data Acquisition Subsystem
FEATURES * Fault Protected 16-Channel 12-Bit A/D Converter with Sample & Hold, Reference, Clock and 3-State Outputs * Fast Conversion, less than 15S * 2's Complement and Serial Data Output * Remote Analog Ground Sensing * Overvoltage Protected Input (50 V over the Supply Voltages) * Precision Reference for Long Term Stability and Low Gain T.C. * Guaranteed Linearity Over Temperature * Guaranteed Performance at +12/-5 V, 12 & 15 V * Low Power (7 mW per Channel Typical) * Parallel Version: MP3276 * 32 Channel Version: MP3274
GENERAL DESCRIPTION
The MP3275 is a complete 16-channel, 12-bit Data Acquisition Subsystem with serial data port. Implemented using an advanced BiCMOS process, the converter combines a 16-channel passive overvoltage-protected multiplexer instrumentation amp, a sample & hold, a SAR, a 12-bit decoded D/A, a comparator, a precision reference and the control logic to achieve an accurate conversion in less than 15s, and a mux/instrumentation amp settling period of less than 10s. A unique input design provides input overvoltage protection to 50 V over the supply voltages. The circuit design can allow for an overvoltage condition on unselected channels without disrupting the measured channel or operation of the MP3275! The internal 4 V reference has sufficient output current to provide other system reference needs. Precision thin film scaling and offset resistors are laser trimmed to provide for less than 2 LSB INL for +10 V inputs on all channels. In addition, the MP3275 will output either full scale (0111 ....) for overrange and - full scale (1000....) for underrange conditions. This greatly simplifies microprocessor software development.
SIMPLIFIED BLOCK DIAGRAM
GND REF. VDD VCC AGND
AB0-3 (4 pins) AIN0-15 (16 pins) AGND2
4 16
16 Ch. MUX
- + REF IN /2 VREF VDAC
Comp
REF OUT
4V REF
CLK
12 SAR 12
AGND3
Control Logic
Latch/ Shift Register 3-State Driver
SDC
DGND VEE
WR
RD
STS CS ADEN STL
DGND
SDO
Rev. 4.00 1
MP3275
ORDERING INFORMATION
Package Type
PQFP
Temperature Range
-40 to +85C
Part No.
MP3275AE
DNL (LSB)
2
INL (LSB)
2
PIN CONFIGURATIONS
33
23
34
See the following page for pin numbers and descriptions
Index
22
44
12
1
11
44 Pin PQFP Q44
Rev. 4.00 2
MP3275
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NAME VEE AIN12 AIN13 AIN14 AIN15 GNDREF AGND REF AGND3 DGND SDC N/C N/C N/C N/C SDO STS STL DGND RD CS WR DESCRIPTION - Analog Supply. -4.75 To - 16.5 Channel 12 Analog Input, 1100 Channel 13 Analog Input, 1101 Channel 14 Analog Input, 1110 Channel 15 Analog Input, 1111 + Input To Mux / Instrumentation Amp A/D Section Analog Ground 29 Reference Output 30 Reference Analog Ground 31 Digital Logic And Output Ground 32 Serial Data Clock 33 No Connection 34 No Connection 35 No Connection 36 No Connection 37 Serial Data Out 38 Conversion Status, Converting=1 39 Input Settling Period State = 1 40 Digital Gnd, Low Current 41 Enable Serial Data Out 42 Chip Select 43 Input Address And Conversion Control 44 AIN9 AIN10 AIN11 Channel 9 Analog Input, 1001 Channel 10 Analog Input, 1010 Channel 11 Analog Input, 1011 AIN4 AIN5 AIN6 AIN7 AGND2 AIN8 N/C Channel 4 Analog Input, 0100 Channel 5 Analog Input, 0101 Channel 6 Analog Input, 0110 Channel 7 Analog Input, 0111 Agnd For Input Mux Section Channel 7 Analog Input, 1000 No Connection VCC AIN0 AIN1 AIN2 AIN3 N/C Analog + Supply, +11.4 to + 16.5 Volts Channel 0 Analog Input, 0000 Channel 1 Analog Input, 0001 Channel 2 Analog Input, 0010 Channel 3 Analog Input, 0011 No Connection PIN NO. 23 24 25 26 27 28 NAME ADEN AB3 AB2 AB1 AB0 VDD DESCRIPTION Address Update Enable=1, Ignore=0 Input Address Bit 3, (MSB) Input Address Bit 2 Input Address Bit 1 Input Address Bit 0, (LSB) Digital Logic & Output Supply, +4.75 to + 5.25 Volts
Rev. 4.00 3
MP3275
ELECTRICAL CHARACTERISTICS TABLE
Unless Otherwise Specified: VDD = 5 V, VCC = 15 V, VEE = -15 V, GNDRef = 0 V, TA = 25C
25C Typ Tmin to Tmax Min Max 12
Parameter Resolution (All Grades) KEY FEATURES Resolution Conversion Time, Per Channel ACCURACY (A Grade)1
Symbol N
Min 12
Max
Units
Test Conditions/Comments Bits
12 tCONVR 15
12 15
Bits s Refer to Table 6. for output coding
Differential Non-Linearity Integral Non-Linearity Zero Code Error Full Scale Error POWER SUPPLY REJECTION
DNL INL EZS EFS
3/4 1
2 2
2 2 10 0.5
LSB LSB LSB %
2 5 0.1 0.35
Best Fit Line (Max INL - Min INL)/2 fff to 000 [hex] transition VREFIN = 4.000 V Max change in Full Scale Calibration
VCC = 15 V 1.5 V or 12 V 0.6 V VDD = 5 V 0.25 V VEE = -15 V 1.5 V or -12 V 0.6 V -5 V 0.25 V REFERENCE VOLTAGES Voltage Output Ref. Source Current Ref. Sink Current ANALOG INPUT Input Voltage Range3 Ground Reference CM Range2 CM RR Input Resistance Input Capacitance2 Aperture Delay2 Channel-to-Channel Isolation2 DIGITAL INPUTS WR, RD AB0-AB4, ADEN, SDC Logical "1" Voltage Logical "0" Voltage Leakage Currents4 Input Capacitance2 VIH VIL IIN 2.4 -0.5 -5 5 VIN GND Ref. -10 -3 RIN CIN tAP 100 TBD 130 5 180 -80 VREF(+) 3.975 3.0 4.0 4.0 20
1 2 1
1 2.5 1
LSB LSB LSB
4.025
3.970 3.0
4.030
V mA A
10 +3
-10 -3 100
10 3
V V LSB/V k pF ns dB
-70
From WR low to high after STL high to low DC
5.5 0.8 5
2.4 -0.5 -10
5.5 0.8 10
V V A pF
VIN=GND to VDD
Rev. 4.00 4
MP3275
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Description DIGITAL OUTPUTS (Data Format 2's Complement) SDO, STS, STL Logical "1" Voltage Logical "0" Voltage Tristate Leakage POWER SUPPLIES Operating Range VDD VCC VEE Operating Current IDD ICC IEE Power Dissipation VOH VOL IOZ 4.0 -5 0.4 5 2.4 -5 0.4 5 V V A Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Conditions COUT=15 pF
ISOURCE = 0.5 mA ISINK = 1.6 mA VOUT=GND to VDD
+4.5 +11.4 -4.75 2 5 1.5 110
+5.5 +16.5 -16.5 7 8 3 200
+4.5 +11.4 -4.75
+5.5 +16.5 -16.5 7 8 3 200
V V V mA mA mA mW
Tested at -11.4 and -16.5 only
NOTES 1 Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the ideal code width is the DNL error. The INL error is the maximum distance (in LSB's) from the best fit line to any transition voltage 2 Guaranteed. Not tested. 3 All channel input pins and ground reference pin have protection which becomes active above 60 V. 4 All digital inputs have diodes to VDD and AGND. Input DC currents will not exceed specified limits for any input voltage between AGND and VDD.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +16.5 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to -16.5 V VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V Digital Inputs or Outputs (WR, RD, CS, AB0-AB4, ADEN, SDC) to DGND . . . . . . . . . . . . . . . . . . -0.5 V to VDD +0.5 V Analog Inputs (AIN0 - AIN15, GND REF) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
1
REF OUT . . . . . . . . . . . . . . . . . . . Indefinite short to DGND, Momentary short to VCC Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Package Power Dissipation Rating to 75C PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . 10 mW/C Lead Temperature, Soldering . . . . . . . . . . . . 300C, 10 Sec Storage Temperature (Ceramic) . . . . . . . . -65C to +150C
NOTES: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All logic inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s.
Rev. 4.00 5
MP3275
PRODUCT INFORMATION
Basic Description
The MP3275 is a fault protected data acquisition subsystem available in monolithic form. This product contains all of the circuitry necessary to acquire 16 channels of quasi differential or single-ended analog signals at 10 V input range and 15kHz bandwidth. Connections to power, the analog input signals and the digital system are all that is required. The MP3275's input circuitry is protected against active input signals present with the MP3275 power off. This is also the case for any channel exceeding the MP3275 analog input dynamic range without interfering with the channel being digitized. The channel address and channel conversion can be managed in two ways: random channel conversion or same channel conversion. Circuitry on the chip adds a MUX/instrumentation amp settling delay of 10s max, when a new channel is selected (ADEN = 1). Conversion start is initiated without delay for the single-channel case (ADEN = 0). Data is available in serial format.
TIMING
Control and Timing Considerations
The MP3275 can be operated in the stand-alone mode, with one line for control and everything else hard-wired; or under microprocessor control, where changes can be made dynamically. There are 4 control lines: ADEN, WR, CS and RD with their functions described in Table 1.
CS
WR
RD
ADEN
Data
STL
STS
Comments
ADC Channel Select and Start Convert (See Figure 1. and Table 2.) 1 0 0 0 0 0 0 X 0 1 1 X 1 1 1 1 1 1 X 0 1 X X X X -- Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 1 0 0 0 0 0 0 No operation No operation if ADEN = 0 Input MUX channel selected, STL set on WR falling edge MUX select disabled Start convert on WR rising edge Start convert on STL falling edge STS goes low at end of conversion
Read ADC Data (See Figure 2. and Table 3.) 0 0 0 0 0 0 0 1 X X 1 X 0 X 0 0 0 X X X X X 0 X -- ADC Hi-Z Hi-Z Last ADC Hi-Z ADC 0 0 0 0 1 0 0 0 0 0 1 0 SDO enabled Data from previous conversion on SDO SDO disabled SDO/RD disabled while STS high Data from last conversion on SDO STL, MUX select disabled with ADEN = 0, SDO disabled on STS rising edge New data appears on SDO on falling edge of STS
Note 1: If RD = 1, SDO remain high impedance. It is recommended that RD will not change during a conversion in order to reduce noise. It is further recommended that RD = 1 during conversion to reject any noise present on the SDO.
Table 1. Logic Truth Table
Rev. 4.00 6
MP3275
The MP3275 is easily interfaced to a wide variety of digital systems. Discussion of the timing requirements of the MP3275 control signals follows.
Figure 1. shows a complete timing diagram for the MP3275 convert start operation.
WR is used to initiate a conversion. A conversion is started by taking WR low, then high again (conversion is enabled on the rising edge of WR). There are two possible conditions that will affect conversion timing. 1. ADEN = 1. At the falling edge of WR, the input channel is determined by the data present on the address bits. The track and hold begins to settle after which STL returns low, indicating that the multiplexer, buffer amp, and sample/hold have settled to less than 1/2 LSB of final value. If the rising edge of WR returns high prior to STL going low, conversion will begin on the falling edge of STL. If the rising edge of WR is delayed until after STL returns low, the input signal is sampled and the conversion is started at the rising edge of WR giving the user better control of the sampling time. 2. ADEN = 0. At the falling edge of WR the data present at the address is ignored and the channel selected during the preTime Interval
vious conversion remains selected. In this case the track and hold settling time is omitted and STL never goes high. At the rising edge of WR the input signal is sampled, and conversion is started. There are two possible states that the data output could be in during a conversion. 1. If RD is held high during a conversion the output would remain high impedance throughout the conversion. This is the preferred method of operation as any noise present on SDO is rejected. 2. If RD is held low during a conversion, the data present SDO will be from the previous conversion until the present conversion is completed, when STS returns low. The data from the new conversion will be available through SDO. The state of RD should not change during a conversion. Once a conversion is started and the STL or STS line goes high, convert start commands will be ignored until the conversion cycle is completed. The SDO output buffer cannot be enabled during conversion. In addition, all input and output changes during conversion can introduce noise, and should be avoided when possible.
ADC Write Timing ADC Control Timing Address to WR Set-Up Time Address to WR Hold Time WR Pulse Width ADEN to WR Set-Up Time ADC Conversion Timing WR to STL Delay STL High (Settling Period) STL to STS Low (Converting) WR to STS High (ADEN = 0) WR to STS Low (ADEN = 1) STS High to SDO Relinquish Time STS Low to Data Valid (RD = 0)
25C
Tmin to Tmax
Limits
Comments/Test Conditions
t3 t4 t5 t6
0 0 80
0 0 80 0
ns min ns min ns min ns min
t7 t8 t9 t12 t10 t13 t14
150 10 15 200 15 150 50
150 15 20 250 20 150 50
ns max s max s max ns max s max ns max ns max
Load ckt of Figure 5, CL = 20 pF, ADEN = 1 Load ckt of Figure 5, CL = 20 pF Load ckt of Figure 5, CL = 20 pF STL = 0 when ADEN = 0 Load ckt of Figure 4 Load ckt of Figure 3, CL = 20 pF
Table 2. ADC Write Timing (See Figure 1.)
Rev. 4.00 7
MP3275
WR t5 t3 ADDRESS t4
ADEN t6 STL t7 STS t8 t 12 t 10 t 11 SDO RD = 0 SDO RD = 1 HIGH Z Previous ADC Data t 13 New ADC Data t9 t 14
Figure 1. Timing for ADC Channel Select Start Conversion
ADC Read Timing RD to Data Valid Delay SDO Relinquish Time after RD High RD Pulse Width
Time Interval t17 t18 t19
25C 100 150 100 100
Tmin to Tmax 150 200 150 150
Limits ns max ns max ns max ns min
Comments/Test Conditions Load ckt of Figure 3., CL = 20 pF Load ckt of Figure 3., CL = 100 pF Load ckt of Figure 4.
Table 3. ADC Read Timing (See Figure 2.)
RD
DATA t 17
Valid t 18
Figure 2. Timing for ADC Read
Rev. 4.00 8
MP3275
+5 V 3k +5 V 3k
DB N DB N
3k
DB N CL
3k 10pF
DB N
CL
10pF
a. High-Z to VON
b. High-Z to VOL
a. VON to High-Z
b. VOL to High-Z
Figure 3. Load Circuit for Data Access Time Test
Figure 4. Load Circuit for Bus Relinquish Time Test
STL, STS CL DGND
Figure 5. Load Circuit for WR to STS Delay
Serial Data Output
The serial data output sequence is MSB (DB11) first to LSB (DB0) last. The MSB (DB11) data bit appears at SDO when STS goes low. The second most significant bit appears at SDO on the SDC high-to-low transition next. The LSB (DB0) is present at SDO on the 11th SDC high-to-low transition. Further information regarding serial control and timing is shown in Figure 6., Table 4. and Table 5.
STS
For a minimum interconnect serial environment, the channel address state can be generated in at least two ways, using an address counter, or using an address serial to parallel converter. WR can then be used as the counter clock or shift register load signal as well as the A/D converter start convert signal on the rising edge. (Note that the falling edge loads the address present at the address port.)
t21 SDC
t22
SDO
SDC should be in a high state during the STS high period. SDC can make the first high to low transition after t21.
Rev. 4.00 9
CCCCC CCCCC
See Table 4
t20 DB10
DB11 (MSB)
Figure 6. Serial Data Mode Timing
MP3275
Serial Data Output Timing STS low to SDO Valid, RD = 0 Minimum clock high pulse width SDC low to data valid delay Time Interval t20 t21 t22 25C 50 50 150 200 Tmin to Tmax 50 80 200 250 Limits ns max ns max ns max ns max Comments/Test Conditions Load Ckt 4 of Figure 3. Load ckt of Figure 3., CL = 20pF Load ckt of Figure 3., CL = 100pF
Table 4. Serial Data Output Mode Timing (See Figure 6.)
WR
RD
ADEN
Data
STL
STS
DB0/SDC
Comments
ADC Channel Select and Start Convert 0 1 1 1 1 1 1 1 1 0 1 X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 1 0 0 0 0 0 X X X X X X No operation if ADEN = 0 Input MUX channel selected, STL set on falling edge of WR MUX select disabled Start convert on WR rising edge Start convert on STL falling edge STS goes low at end of conversion
Read ADC Data (See Figure 6. and Table 4.) 1 X X X X X X 1 X 0 0 0 0 X 0 0 X X X X X X X X 0 X --
MSB (DB11)
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
1 1 0 X X 1 1
DB10 DB10 DB10 DB9 Hi-Z Hi-Z Hi-Z
MSB (DB11)
Serial output (SDO) and serial clock input (SDC) enabled MSB data available at SDO Next significant bit shifted out to SDO No Operation No Operation Next significant bit shifted out to SDO Data outputs/SDC input disabled Data outputs/RD disabled when STS = 1 STL, MUX select disabled when ADEN = 0 New data appears at SDO on falling edge of STS
Note 1: If RD = 1, data outputs remain high impedance. It is recommended that RD will not change during a conversion in order to reduce noise. It is further recommended that RD = 1 during conversion to reject any noise present on the data bus.
Table 5. Logic Truth Table - Serial Data Output
2's Complement Output Code (Hexidecimal) 0111 0000 1111 1000 1111 0000 1111 0000 1110 (7fe) to 0000 (000) to 1111 (fff) to 0000(800) to 0111 0000 0000 1000 1111 0000 0000 0000 1111 (7ff) 0001 (001) 0000 (000) 0001 (801)
Ideal Transition Voltage +FS - 1 1/2 LSB 0 V +1/2 LSB 0 V -1/2 LSB -FS +1/2 LSB
Table 6. Key Output Codes vs. Input Voltage (2's Complement Code)
Rev. 4.00 10
MP3275
APPLICATION INFORMATION
The MP3275 is a complete A/D converter system, with its own built-in reference and clock. It may be used by itself ("standalone" operation), or it may be interfaced with a microprocessor. Successful application of the MP3275 requires careful attention to four main areas: 1) 2) 3) 4) Physical layout. Connection/Trimming according to mode of operation. Conditioning of input signals. Control and Timing considerations.
Ground Reference
The ground reference pin can be used for remote ground sensing of a common mode input signal with a maximum 6 V p-p around AGND. This common input can also be used to dither each input's "zero". By averaging multiple conversions digitally, higher resolution for each input conversion can be obtained. Patterns for this dither can be a ramp, a stair step, or white noise.
Physical Layout
The 12-bit accuracy of the MP3275 represents a dynamic range of 72dB. Precautions must be taken to avoid any interfering signals, whether conducted or radiated, to assure that this is not degraded. * Avoid placing the chip and its analog signals near logic traces. In general, using a double sided printed circuit card with a good ground plane on the component side is recommended. Routing analog signals between ground traces will help isolate digital control logic. If these lines cross, do so at right angles. The GND Ref. is the positive terminal of the MUX/Instrumentation amplifier and will provide common mode noise rejection. It should be close to and shielded together with the channel inputs in order to take advantage of this feature. Power supplies should be quiet and well regulated. Grounds should be tied together at the package and back to the system ground with a single path. Bypass the supplies at the device with a 0.01 to 0.1F ceramic cap and a 10-47 F tantalum type, in parallel.
130k 1 of 16 COMP 26k
GND Ref. 130k 26k 1/2 VREF VDAC 12
S A R
*
Figure 7. Equivalent Input Circuit
Quasi Differential Sampling
Method 1
"Stand-Alone" Operation
The MP3275 can be used in "stand-alone" operation, which is useful in systems not requiring full computer bus interface capability. For this operation, CS = 0, ADEN = 1, and conversion is controlled by WR. The 3-state buffer SDO is enabled when RD goes low. There are two possible conditions that the 3-state buffer could be in during a conversion. If RD goes low prior to WR the output buffer is enabled and the data from the previous conversion is available at the outputs during STL = 1. At the end of the present conversion which is initiated at the rising edge of WR, STS returns low and the new conversion result is placed on the output data buffer. If WR goes low prior to RD, the data buffer remains in a high impedance state and conversion is initiated at the rising edge of WR. Upon the end of the conversion the STS returns low and the conversion result is placed on the output data buffers. Rev. 4.00 11
For remote ground sensing where the remote ground does not change more than 3 V from the A/D ground, connect GND Ref to the remote ground.
Method 2
Where Method 1 applies to each channel or group of channels, add a mux to allow connecting the appropriate ground to GND Ref.
Method 3
Use two parts. Tie both GND Ref pins together and connect this node to the "common" remote GND. Control the sample point by connecting each STL through an "OR" gate whose output is "NAND" connect with WR (inverted WR). Use this output as WR to both WR inputs. By controlling the WR, sample delay differences between the two converters is minimized. Two parts from the same date code will further minimize this difference. Treat one A/D as the (+) terminal and the other as the (-) terminal of the differential signal. Now the difference can be taken digitally.
MP3275
44 LEAD PLASTIC QUAD FLAT PACK (14mm x 14mm PQFP, METRIC) Q44
D D1 33 23
34
22
D1 D
44
12
1 B A2 C e
11
A A1
L
MILLIMETERS SYMBOL A A1 A2 B C D D1 e L MIN -- 0.25 2.6 0.3 0.13 16.95 13.9 MAX 3.15 -- 2.8 0.4 0.23 17.45 14.1
INCHES MIN -- 0.01 0.102 0.012 0.005 0.667 0.547 MAX 0.124 -- 0.110 0.016 0.009 0.687 0.555
1.00 BSC 0.65 0 1.03 7
0.039 BSC 0.026 0 0.040 7
Coplanarity = 4 mil max.
Rev. 4.00 12
MP3275 Notes
Rev. 4.00 13
MP3275 Notes
Rev. 4.00 14
MP3275 Notes
Rev. 4.00 15
MP3275
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 4.00 16

▲Up To Search▲

Price & Availability of MP3275

	To Download MP3275 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .